`timescale 1ns/1ps

module tb;

	logic clk;
	logic rstn;

	logic x3;
	logic x26;
	logic x27;

	always_comb begin
		x3 = tb.u_LilyRiscv_top.u_LilyRiscv.u_regs.GPR[3];
		x26 = tb.u_LilyRiscv_top.u_LilyRiscv.u_regs.GPR[26];
		x27 = tb.u_LilyRiscv_top.u_LilyRiscv.u_regs.GPR[27];
	end
	
	initial begin : clk_gen
		clk = 1'b1;
		forever
			#5 clk = ~clk;
	end
	
	initial begin
		rstn <= 1'b0;
		#30;
		rstn <= 1'b1;	
	end
	
	//rom 初始值
	initial begin
		$readmemh("../../sim/inst_data.txt", tb.u_LilyRiscv_top.u_rom.rom_mem);
	end


	integer ii;
	initial begin
 		wait(x26 == 32'b1);
		
		#100;
		if(x27 == 32'b1) begin
			$display("############################");
			$display("########  pass  !!!#########");
			$display("############################");
		end
		else begin
			$display("############################");
			$display("########  fail  !!!#########");
			$display("############################");
			$display("fail testnum = %2d", x3);
			for(ii = 0; ii < 32; ii ++)begin
				$display("x%2d register value is %d", ii, tb.u_LilyRiscv_top.u_LilyRiscv.u_regs.GPR[ii]);	
			end	
		end
		$finish();
	end
	
	LilyRiscv_top u_LilyRiscv_top(
		.clk   		(clk),
		.rstn 		(rstn)
	);

endmodule : tb